An image display device, for example, a liquid crystal display or other image device display having fixed pixels, as is well known, has an effective pixel area in which a plurality of pixel circuits (hereinafter simply referred to as “pixels”) are arrayed in a matrix and in which three primary colors are assigned to the pixels in a predetermined array.
Each pixel of the liquid crystal display, while not particularly shown, is comprised of a pixel select element constituted by a thin film transistor (TFT), a liquid crystal cell having a pixel electrode connected to a drain electrode (or a source electrode) of the TFT, and a storage capacitor having one electrode connected to the drain electrode of the TFT.
These pixels have scanning lines laid along the pixel array direction of the pixel rows (hereinafter also referred to as “pixel lines”) and signal lines referred to as data lines laid along the pixel array direction of the pixel columns. Gate electrodes of the TFTs of the pixels are connected to the same scanning line in units of pixel rows, while source electrodes (or drain electrodes) thereof are connected to the same signal line in units of pixel columns.
Such liquid crystal displays and other image display devices are becoming higher in definition year by year. The load capacitances of the scanning lines and the signal lines are increasing along with this.
Further, the video signal of the existing NTSC (National Television System Committee) system is set in its screen display period to a frequency of 60 Hz per field (about 16.7 ms in terms of time) and a frequency of 30 Hz per frame (about 33.3 ms in terms of time). Accordingly, when the number of pixel lines increases accompanying higher definition, the time assigned to the display of one pixel line becomes short. The display period of this one pixel line is a period excluding the horizontal blanking period of a head portion in one horizontal scanning (1H) period as referred to in the NTSC video signal format.
In a high definition image display device, when a group of pixels of the effective pixel area is successively and repeatedly displayed for each of the three primary colors, the short line display period and the increased load capacitance of the signal lines explained above result in insufficient writing of the pixel data within a predetermined time and the inability to express colors of a predetermined luminance.
Particularly, in a liquid crystal display, a liquid crystal layer sometimes deteriorates when an electric field having the same orientation is applied to the liquid crystal layer for a long time. From the viewpoint of preventing this, the method of driving by inverting the polarity of the pixel data for each pixel line is the general practice. For this reason, in a liquid crystal display, on average, it is necessary to change the signal line potential to about 2 times the pixel data. Since a long time is taken for changing this large potential difference, the insufficiency of the writing capacity of pixel data accompanying the higher definition has become remarkable.
FIG. 7A and FIG. 7B show waveforms of pulses for writing pixel data into signal lines. Here, FIG. 7A is a write pulse waveform diagram of a liquid crystal display having a low resolution, and FIG. 7B is a write pulse waveform diagram of a liquid crystal display having a high resolution.
When the resolution of the display is low, the time duration of the permission pulse Pw1 for the supply of data to the signal line is, for example, 12 μs which is relatively long. The pixel data is supplied to the signal line from a rising edge of this permission pulse Pw1. The potential 100 of the signal line starts to rise from that time and reaches a desired potential in accordance with a CR time constant determined according to the load capacitance of the signal line. A time Tpc required for charging this signal line is sufficiently small in comparison with the pulse time duration (12 μs).
When the resolution of the display becomes high, however, the load capacitance abruptly increases and the CR time constant of the interconnects becomes high as explained before. Therefore, the situation arises in which the waveform becomes dull in accordance with the load capacitance, like a signal line potential 100A or 100B shown in FIG. 7A, the signal line potential cannot reach the predetermined write potential within the predetermined write time, and the signal line cannot be sufficiently charged.
In addition, as shown in FIG. 7B, the write time per se becomes, for example 5, μs, which is short, and therefore, even if the load capacitance does not increase very much, sufficient charging of the signal line becomes difficult.
In order to eliminate the insufficiency in the writing operation, the technique of precharging the signal line for boosting the signal line potential to an intermediate potential preceding the writing of the pixel data is known (see, for example, Japanese Patent Publications: Japanese Patent Publication (A) No. H10-011032 or Japanese Patent Publication (A) No. 2003-177720).
When employing this technique of precharging a signal line, as shown in FIG. 7C, if a signal line potential 102 can reach a certain intermediate potential by the previously performed precharging (waveform 101) at the starting point of the rising edge of a permission pulse Pw2 of the supply of data to the signal line, it becomes possible to make the signal line potential 102 reach the desired potential within a short permission pulse time.
The precharge waveforms are drawn superposed at the time of charging of the signal line by the pixel data in FIG. 7C for convenience sake, but as disclosed in the above two publications, the signal line is frequently precharged in the horizontal blanking period located at the head portion of one horizontal scanning period (1H).
Incidentally, the shortening of the write time accompanying the higher definition of the display described above occurs because the drive clock frequency becomes high in addition to the increase of pixel number of one pixel line. Therefore, the horizontal blanking period also becomes short, and sometimes there is no longer a sufficient precharging time. Further, the amount to be precharged in the signal line increases, and therefore the precharging in such a horizontal blanking period has become difficult. Accordingly, realistically, there are actual circumstances where the effect of precharging as shown in FIG. 7C are not sufficiently obtained with a high definition display.
An explanation of this is given by a more detailed example using FIG. 8A, in a low resolution liquid crystal display device having, for example, 480×320 pixels or less; as shown in FIG. 8A, separately from the interior of a horizontal drive circuit 111 arranged at one end of an effective pixel region 110, a precharge circuit 112 is provided on an opposite side of the signal line 113. The horizontal drive circuit 111 is provided with a select switch for controlling an output of the pixel data constituted by a CMOS transfer gate TG1 for each signal line 113. In the same way, the precharge circuit 112 is provided with a CMOS transfer gate TG2. The supply of the precharge voltage is controlled by this CMOS transfer gate TG2.
FIG. 8B shows details of two CMOS transfer gates. At the time of the horizontal drive of the display, a precharge signal SPC is applied to the signal line 113 of the effective pixel area from the CMOS transfer gate TG2 in the precharge circuit 112, and then a pixel data signal SDT is input to the signal line 113 of the effective pixel area from the CMOS transfer gate TG1 of the horizontal drive circuit side.
In a high resolution liquid crystal display device having 640×480 pixels or more corresponding to the VGA, however, as previously explained, the drive frequency for driving the device becomes high and, at the same time, the load capacitance of the interconnects of the display device increases. Therefore, the signal line potential no longer reaches the expected intermediate potential in the predetermined write time, an insufficient write operation occurs, and as a result a clear image is no longer obtained.
In this case, in order to perform a stable precharge, the size of the CMOS transfer gate TG2 must be increased, so the area occupied by the precharge circuit 112 increases. In addition, the impedance of the signal line 113 must be lowered, the width of the interconnects must be broadened, and so on. Due to these problems, the percentage of substrate area occupied by the interconnects for precharging increases in the same way as above. Further, in package precharging, a high precharging capability is required; therefore, as shown in the overall block diagram in FIG. 9, the horizontal drive circuit (HDRV) 111 and the precharge circuit (PCH) 112 must be separately provided or one of two horizontal drive circuits must be equipped with the precharge function, so the increase of the area penalty of the precharge circuit becomes a problem.
Further, the lowest limit of the precharging sometimes differs for each of the three primary colors. In such a case, with package precharging in the horizontal blanking period, the problem of wasteful precharging for some of the colors arises.